The present invention relates to a solid-state image sensing apparatus and a method of operating the same and, more particularly, to a solid-state image sensing apparatus widely used in an image input apparatus, such as a video camera and a digital still camera, and a method of driving the solid-state image sensing apparatus.
Recently, technique for reducing the cell size of a photoelectric conversion element has been actively developed for increasing resolution using refining processing. At the same time, since the level of the output signal from the photoelectric conversion element decreases as the cell size of the photoelectric conversion element is reduced, an amplification-type photoelectric conversion apparatus, capable of amplifying a photo-charge signal then outputting it, has been getting attention.
As such amplification-type photoelectric conversion apparatuses, there are metal oxide semiconductor (MOS) type, an amplified MOS imager (AMI), a charge modulation device (CMD), and a base stored image sensor (BASIS), for instance, but not a conventional charge-coupled device (CCD) type. Among these, in a MOS-type photoelectric conversion apparatus, photo-electrons generated by a photodiode, as a photoelectric conversion element, are collected at the gate of a MOS transistor, and the charge at the gate is amplified using a change in potential at the gate caused by the charge and outputted to an output unit in accordance with a driving signal from an operation circuit. Further, a complementary MOS (CMOS) type photoelectric conversion apparatus, among MOS-type photoelectric conversion apparatuses, can be manufactured in CMOS logic LSI processing, in addition, peripheral circuits can be integrally formed on the same chip easily. Furthermore, the CMOS-type photoelectric conversion apparatus can be operated with a low voltage, which saves electrical energy; therefore, it is anticipated as a useful image sensor for a portable device. Since photodiodes, i.e., photoelectric conversion elements, of the CMOS-type image sensor and their peripheral circuits are made in the CMOS logic LSI processing, the photodiodes and the peripheral circuits are collectively called a CMOS image sensor.
The CMOS image sensor has one or more MOS field effect transistors (FETs) in each cell (pixel). Especially, the CMOS image sensor having a MOS FET for amplification (referred to as “MOS amplifier” hereinafter) whose gate accumulates photo-charge in each pixel can read a carrier signal generated by the photoelectric conversion element in a predetermined period, therefore, is used for a high-sensitive image sensing apparatus.
In such a CMOS image sensor, the output signal level is increased by amplifying photo-charge using the MOS amplifier provided in each pixel; however, at the same time, irregularity in threshold voltages Vth and gain of the MOS amplifier causes deterioration of the S/N ratio. Especially, it is not possible to restrain irregularity in the threshold voltages Vth below several millivolts under the current manufacturing technique. Further, the saturation voltage of the MOS amplifier is in some volts range since the saturation voltage depends upon the voltage of the power supply. Therefore, the S/N ratio is a three-digit number at best, and it is very difficult to achieve 70 to 80 dB, which is the demand of the market.
In order to overcome the above problem, a read circuit using a capacitive clamp circuit, as shown in FIG. 17, is disclosed in the Japanese Patent Application Laid-Open No. 4-61573. FIG. 18 shows an equivalent circuit of a pixel of a solid state image sensing apparatus disclosed in the above reference. Below, the operation of the image sensing apparatus is briefly explained with reference to the equivalent circuit of a pixel shown in FIG. 18 and the timing chart shown in FIG. 19.
Referring to FIG. 18, in advance of reading of photo-charge from a photodiode D1, signals ΦCR1, ΦCR2 and ΦCS1 at time t31p are changed to high, thereby a MOS switch Q16 is turned on; in turn, a vertical signal line VL3 becomes a ground level, and capacitors C1 and C3 are reset to a voltage VSS. Thereafter, a signal ΦCR1 is changed to a low level at time t32p, further, a reset signal ΦRS is changed to a high level, thereby the gate of the MOS amplifier Q2 is reset to a voltage VRS.
Then, at time t33p the reset signal ΦRS is changed to a low level and a signal ΦV3 is changed to high, thereby a MOS FET Q3 for selection (referred to as “MOS selector” hereinafter) is turned on, and an operation voltage VDD is provided to the drain of the MOS amplifier Q2. Accordingly, a voltage VN corresponding to the gate voltage of the MOS amplifier Q2 appears on the vertical signal line VL3 (noise signal).
Next, the signal ΦCR2 is changed to low at time t34p, which puts the output side of the capacitor C1 and one electrode of the capacitor C3 in a floating state. At this time, the signal ΦV3 is changed to low to turn the MOS selector Q3 off. Then, the signal ΦCR1 is changed to high to reset the vertical signal line VL3, thereby the potential of the output side of the capacitor C1 and one electrode of the capacitor C3 becomes a potential, VSS−VN′, that is the bias voltage VSS is reduced by a voltage VN′, which is a part of the voltage VN, corresponding to the ratio of the capacitance of the capacitor C1 to the total capacitance of the capacitors C1 and C3. Here, VN′ is expressed by the following equation (1).VN′=C1×VN/(C1+C3)  (1)
Next at time t35p, the signal ΦCR1 is changed to low, the signal ΦV3, applied to the gate of the MOS selector Q3, and a signal ΦVG, applied to the gate of a MOS FET Q1 for transferring photo-charge (referred to as “MOS switch” hereinafter), are changed to high. Accordingly, the MOS switch Q1 is turned on, and the photo-charge generated by the photodiode D1 is transferred to an input capacitor CP. At the same time, the MOS selector Q3 is turned on, and the operation voltage VDD is provided to the drain of the MOS amplifier Q2 via the MOS selector Q3, thereby a voltage VS, corresponding to the gate voltage of the MOS amplifier Q2 appears on the vertical signal line VL3 (photo-charge signal).
With the aforesaid operation, a voltage across the capacitor C1 is increased by a voltage VS′, which is a part of the voltage VS, corresponding to the ratio of the capacitance of the capacitor C1 to the total capacitance of the capacitors C1 and C3, and becomes VSS−VN′+VS′.
Here, the voltage VS′ is expressed by the following equation (2), similarly to the voltage VN′.VS′=C1×VS/(C1+C3)  (2)
Therefore, the final voltage, VC3, across the capacitor C3 is,VC3=VSS−C1×(VN−VS)/(C1+C3)  (3)Thus, a high S/N signal, from which irregularity in the thresholds Vth of a MOS FET for resetting and of a MOS amplifier is reduced, is obtained as seen in the second term, (VN−VS).
In improving the S/N ratio of a CMOS image sensor, while taking measures to reduce fixed pattern noise by providing an image sensing apparatus and method of driving the apparatus as described above, it is also necessary to increase the maximum allowable charge (Qsat) so as to improve the S/N ratio with regard to random noise which occurs when displaying a moving image.
In a solid-state image sensing apparatus having a photoelectric conversion element, a transfer switch, and a field effect transistor (FET) for amplification whose gate accumulates photo-charge from the photoelectric conversion element of each pixel, a capacitance of a capacitor C which is connected to the gate of the FET (corresponding to the capacitor Cp in the aforesaid example) affects the maximum charge capable of being transferred, namely, the maximum allowable charge Qsat, when transferring photo-charge generated by the photoelectric conversion element to the gate of the FET.
The reason for this is as follows. If the charge to be transferred is electrons, relationship Vg (gate voltage)>Vpd (voltage generated by photodiode) should hold for the charge to be transferred. However, since the drop of the gate voltage Vg when unit charge is transferred is inverse-proportional to the capacitance C, if the capacitance C is small, the drop the gate voltage Vg is large in response to a small transferred charge. When the FET is a MOS FET, then the gate capacitance of the MOS FET is also included in the capacitance C. Since the gate capacitance of the MOS FET changes in accordance with its operation state, the maximum allowable charge Qsat changes depending upon the operation state of the MOS FET when transferring charge.
The aforesaid problem is not considered in the conventional operating method. In the conventional operating method as shown in FIG. 19, for instance, when transferring charge by applying a pulse ΦVG to the gate of the MOS switch Q1, the source of the MOS amplifier Q2 connecting to the vertical signal line VL3 is in a floating state, therefore, the operation of the MOS amplifier Q2 is not determined. If the MOS amplifier Q2 is in an on state, since the MOS selector Q3 is also on when transferring charge, the voltage VDD is applied to the drain of the MOS selector Q3, thus the MOS amplifier Q2 is put into the saturation region and the gate capacitance is reduced comparing to a case of operating in the triode (linear) region. Therefore, problems result from unsteadiness of a floating state when reading photo-charge from the photoelectric conversion element and change in a linear operation range of the MOS amplifier Q2.
Further, in order to increase sensitivity upon transferring photo-charge from the capacitor C3 to a common output line, the capacitor C3 needs to have capacitance of several pF. In addition, in order to increase sensitivity, when reading photo-charge from each pixel, which is determined by a part of the second term of equation (3), namely C1/(C1+C3), the capacitor C1 needs to have a capacitance of least several times larger than the capacitance of the capacitor C3. However, due to limitation on the chip size and manufacturing cost, satisfactory sensitivity can not always be obtained.
Furthermore, in the aforesaid method of reading photo-charge, when reading a noise signal, the output side of the capacitor C1 is reset to the voltage VSS, whereas, when reading a photo-charge signal, the output side of the capacitor C1 is in a floating state. In the floating state, for the photodiode D1, the capacitance of the capacitors C1 and C3 connected in parallel becomes the capacitance of the capacitor C1. Therefore, there is no problem if reading operation is performed by taking a sufficiently long time; however, if reading operation is performed in a short time, the initial potential of the vertical signal line when outputting a noise signal and the initial potential of the vertical signal line when outputting a photo-charge signal are different, which makes it difficult to reduce noise at high precision.
In addition, in the aforesaid method of reading signals, the voltage for resetting the vertical signal line VL3 must be sufficient to turn on the MOS amplifier Q2 for every signal level inputted to the gate of the MOS amplifier Q2, thus restricts the reset voltage.
Besides the aforesaid reference, the concept of resetting the vertical signal line VL3 is disclosed in, e.g., the Japanese Patent Application Laid-Open No. 58-48577 and the Japanese Patent Publication No. 5-18309 for preventing interference between pixels, such as leakage of charge, in a photoelectric conversion element having non-destructive reading characteristics.
Operation of the aforesaid references is briefly explained with reference to the block diagram in FIG. 20 showing a sensor area of a solid-state image sensing apparatus disclosed in the foregoing references, a circuit diagram in FIG. 21 showing a horizontal switch circuit, and a timing chart in FIG. 22.
At time t0p, a signal ΦPV1 becomes high, and MOS switches S11 to S7681 which are connected to a vertical signal line V1 of a sensor array Cji are turned on, thereby photo-charges in cells (pixels) C11 to C7681, are outputted to signal output lines B1 to B768.
Slightly after the time t0p, at time t1p, a signal ΦPH1 applied to the horizontal signal line H1 becomes high. Accordingly, MOS switches Q11 to Q132 in a horizontal switch circuit are turned on, thereby photo-charge on the left-most signal output line in each of the 32 sub-groups, each includes 24 signal output lines, of the signal output lines B1 to B768 is outputted to multiplexing output lines A1 to A32. Signals on the multiplexing output lines A1 to A32 are outputted through amplifiers T1 to T32, respectively. Each of the amplifiers T1 to T32 comprises a pair of differential transistors both connected between a common constant current source and ground. To the base of one of the transistors, an analog pixel (photo-charge) signal is inputted, whereas to the base of the other transistor, a dark voltage from a pixel which is shielded from light is inputted. Then an analog signal obtained by subtracting the dark voltage from the analog pixel signal is outputted.
Then, the signal ΦPH1 applied to the horizontal signal line H1 becomes low, and a signal ΦPH2 on a horizontal signal line H2 becomes high at time t2p. Accordingly, the MOS switches Q22, to Q232 in a horizontal switch circuit are turned on, thereby pixel signals on signal output lines which are the second to the left-most lines in the respective 32 sub-groups of signal output lines B1 to B768 are outputted to multiplexing output lines A1 to A32. Similarly, signals to be applied to the horizontal signal lines H3 to H24 sequentially become high, and analog pixel signals of the respective sub-groups are outputted. After the signal ΦPH24 applied to the last horizontal signal line H24 becomes low, the signal ΦPV1 applied to the vertical signal line V1 becomes low, thereby scanning of all the cells connected to the signal line V1 is completed.
Thereafter, before start of reading the cells connected to the signal line V3, a blanking period elapses. During the blanking period, signals ΦPH1 to ΦPH24 applied to the horizontal signal lines H1 to H24 are turned to high, thereby connecting all the signal output lines B1 to B768 to the corresponding output lines A1 to A32. At the same time, a signal ΦPR on a refresh line R is turned to high and MOS switches R1 to R32 are turned on, thereby the multiplexing output lines A1 to A32 are grounded. Accordingly, all the signal output lines B1 to B768 are grounded, and residues of pixel signals remaining from the previous scanning are cleared.
However, there are the following problems in the aforesaid configuration, which will be explained below with reference to FIG. 23. FIG. 23 shows a case of reading pixel signals from the cells connected to the vertical signal line V1. In FIG. 23, a signal voltage of the cell C11 is denoted by VS1, similarly, signal voltages of the cells C21 to C241 are denoted by VS2 to VS24, respectively. Further, parasitic capacitance of the signal output lines B1 to B24 is denoted by C11, parasitic capacitance connected to the base of the transistor connected to the differential transistor T1 is denoted by C21, the common signal output line is A1, and a signal voltage inputted to the base of the transistor is denoted by VSO. Then, a signal voltage VSO′ when a signal on the signal output line B1 is read out is expressed by the following equation (4).VSO′=(C21×VSO+C11×VS1)/(C21+C11)  (4)Further, a signal voltage VSO″ when a signal on the signal output line B2 is read out is expressed by the following equation (5).VSO″=(C21×VSO′+C11×VS2)/(C21+C11)  (5)
In order to prevent interference between adjoining pixels by resetting the gate of the MOS switch R1 by applying the reset pulse ΦPR only during the blanking period, it is necessary to reduce C21×VSO′ in equation (5) by making the capacitance of the capacitor C11 much larger than the capacitance of the capacitor C21. However, when the capacitance of the capacitor C11 is increased, the capacitance upon transferring a signal from a cell also increases, thereby sensitivity decreases.